Chip 설계를 위한 Design Flow에 따른 각 EDA사별 CAD Tool > 컨설턴트 칼럼

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제목	Chip 설계를 위한 Design Flow에 따른 각 EDA사별 CAD Tool
기능 Vendor명 S/W명 VHDL Simulator Synopsys Scirocco Mentor Graphics ModelSim Aldec Active-HDL Co-Simulator Mentor Graphics ModelSim Aldec Active-HDL Verilog Simulator Mentor Graphics ModelSim Cadence Verilog-XL NC-verilog Synopsys VCS Aldec Active-HDL Circuit Simulator AWR Microwave Office Silvaco Smartspice Cadence Spectre Synopsys Star-Hspice Synthesis Synopsys Design Compiler Cadence Build-Gates Synplicity Synplifypro Mentor Graphics Leonardo Place & Route Synopsys Apollo II Mentor Graphics IC station MMIC Design Mentor IC Graph FPGA Design Altera MaxPlus2,QuartusII Xilinx ISE Actel Actel Dynamic Simulation Synopsys Nanosim Static Timing Analysis Synopsys PrimeTime DFT Mentor Graphics DFT Advisor Synopsys DFT Compiler Synopsys BSD Compiler Syntest TurboSeries Schematic Capture Mentor Graphics DA_IC Cadence Composer Silvaco Scholar MyCAD My analog Layout editor Cadence Virtuoso Silvaco Expert My CAD Mychip Station LVS/DRC AWR Microwave Office Mentor Graphics Calibre Cadence Dracula Cadence Diva Synopsys Hercules LPE Synopsys Star-RC Cadence Dracula PCB Design Mentor Graphics DA CSiEDA Win Series

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